Virtual Memory & Page Table Translation

Virtual Memory is one of the most fundamental abstractions in modern operating systems. It provides every process with the illusion of possessing a large, contiguous private address space—protecting application memory while hardware Memory Management Units (MMUs) map virtual pages to physical RAM frames.

1. Summary & Key Takeaways

• Virtual-to-Physical Address Translation: The CPU Memory Management Unit (MMU) splits virtual addresses into a Virtual Page Number (VPN) and a Page Offset.
• Translation Lookaside Buffer (TLB): An ultra-fast hardware cache on the CPU die storing recent page translations.
  • TLB Hit: Translation found in 0 extra memory cycles!
  • TLB Miss: Requires a 4-level page table walk through RAM (~50–100 cycles).
• Page Fault: Occurs when a virtual address references a page not currently resident in physical RAM, forcing the OS kernel to read the page from disk swap space.

2. Interactive Page Table Translation Playground

Use the interactive MMU hardware visualizer below to test TLB Hits, TLB Misses, and Page Faults!

// Hardware MMU Page Table Translation in C++
#include <iostream>
#include <cstdint>

struct PageTableEntry {
    uint64_t physicalFrameNumber : 40;
    uint64_t present : 1;
    uint64_t readWrite : 1;
    uint64_t userSupervisor : 1;
};

uint64_t translateAddress(uint64_t virtualAddr, PageTableEntry* pageTable) {
    uint64_t vpn = (virtualAddr >> 12) & 0xFFFFF; // Extract 20-bit Virtual Page Number
    uint64_t offset = virtualAddr & 0xFFF;         // Extract 12-bit Page Offset (4KB)

    PageTableEntry pte = pageTable[vpn];
    if (!pte.present) {
        throw std::runtime_error("SIGSEGV: Segmentation Fault - Invalid Memory Access!");
    }

    // Physical Address = (PFN << 12) | Offset
    return (pte.physicalFrameNumber << 12) | offset;
}

3. x86_64 4-Level Page Table Translation

Modern 64-bit CPUs use 4-level page tables to map 48-bit virtual addresses to physical RAM frames:

$\text{Virtual Address (48 bits)} \implies \text{PML4 (9 bits)} \to \text{PDPT (9 bits)} \to \text{PD (9 bits)} \to \text{PT (9 bits)} + \text{Offset (12 bits)}$

4. Memory Lookup Latency Matrix